The invention relates to a compensation circuit for an input signal having an offset and to a method for compensating for an offset in an input signal.
Digital modulation methods in telecommunication involve the amplitude, the frequency, or the phase of a signal that has a carrier frequency being modulated in accordance with a data string that is to be transmitted. Frequency modulation or frequency shift keying (FSK) involves keying between different frequencies. In the simplest case, there are two binary statesxe2x80x94zero and onexe2x80x94accordingly, signal transmission requires only two frequencies disposed symmetrically around the carrier frequency.
In modern communication methods, such as Global System for Mobile Communication (GSM), a Gaussian Minimum Shift Keying (GMSK) method is used in which digital information is coded using Gaussian pulses instead of square-wave pulses. The GMSK method is a continuous-phase FSK method. Like GSM, the Digital Enhanced Cordless Telecommunication (DECT) method used for communication in cordless telephones is also an SSK method.
To demodulate a frequency-modulated signal in a demodulator, the carrier frequency is assigned a mid-voltage in the receiver. The output voltage from the demodulator in the receiver is higher than the intermediate voltage when a logic one is transmitted and is lower than the intermediate voltage when a logic zero is transmitted. In the frequency-modulated signal, the carrier frequency is increased by a particular frequency swing to transmit a one and is reduced by a particular frequency swing to transmit a zero.
Tolerances mean that the carrier frequency of the frequency-modulated signal can vary, for example, on account of temperature drifts in a transmitter. This means that the intermediate voltage associated with the carrier frequency can also vary at the output of the demodulator such that a DC voltage offset exists. Tolerances in the receiver or demodulator itself, for example, production-dependent or temperature-dependent tolerances, mean that the intermediate voltage is subject to additional fluctuations. To stipulate a decision threshold that distinguishes a voltage associated with a logic one from a voltage associated with a logic zero, and, hence, distinguishes between the two states, it is necessary to stipulate a threshold voltage that compensates for the intermediate voltage""s DC voltage offset (DC offset).
In prior art communication systems, for example, in the case of the DECT standard, such a threshold voltage is stipulated by virtue of each user data block being preceded by a preamble with a string of 16 bits that alternately contains ones and zeros and is used for DC offset compensation. A simple low-pass filter can be used to ascertain the mean voltage value of such a signal train corresponding to the first 16 bits, and, at the end of the 16-bit preamble, the value so obtained can be stored, for example, as a voltage value on a capacitor. This averaging or the generation of a threshold voltage is normally controlled in the digital baseband chip of a DECT receiver.
The xe2x80x9cBluetoothxe2x80x9d system describes a wireless interface between individual components of information and communication systems for data transmission over short distances. By way of example, peripheral devices such as printer, mouse, keyboard, mobile telephone, modem, etc. can be wirelessly connected to a portable computer. The Bluetooth system operates in the 2.4 gigahertz Industrial Scientific and Medical (ISM) band. In most of the world""s countries, for example, USA and Europe, the ISM band covers the frequency range from 2,400 to 2,483.5 megahertz. In this case, the channels are defined using the formula f=2,402 +n MHz, where f is the carrier frequency of the channel in question and the variable n can assume integer values from 0 to 78.
The problem with the Bluetooth system, which operates using a time slot method, is that the preamble for an access code, which is respectively placed in front of the actual user signal (payload) and normally includes 72 bits, is only 4 bits long. In addition, this 4-bit preamble""s position in time in a bit sequence can vary by up to 10 bits. However, this 4-bit preamble is too short to stipulate a suitable decision threshold for reliably distinguishing between the logic states.
It is a conventional practice to use digital signal processing to determine a decision threshold for the digitized and demodulated data signal in order to determine the switching threshold for Bluetooth. However, the circuits required for such determination are very complex and, depending on the implementation of the digital signal processing, unreliable. U.S. Pat. No. 4,821,292 to Childress discloses a detector circuit that changes over to a shorter time constant during a signal preamble for the purpose of averaging (dotting pattern). Such changeover achieves faster threshold-value readjustment.
It is accordingly an object of the invention to provide a compensation circuit and method for compensating for an offset that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that are suitable for signals having a short preamble.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a compensation circuit for an input signal having an offset, including a filter unit receiving the input signal in a signal flow direction and having a signal path with a first time constant, a signal path with a second time constant, and a signal path with a third time constant, a first switch connected to the signal path with the first time constant and to the signal path with the second time constant for changing the filter unit between the signal path with the first time constant and the signal path with the second time constant, a second switch connected to the signal path with the third time constant for changing the filter unit over to the signal path with the third time constant, a first comparator connected downstream of the filter unit with respect to the signal flow direction, the first comparator having a first output, a second comparator connected downstream of the filter unit with respect to the signal flow direction, the second comparator having a second output, a third comparator connected downstream of the filter unit with respect to the signal flow direction, the third comparator having a third output, a first decoder connected to the first output and to the first switch for controlling the first switch, and a second decoder connected to the second switch and to a respective one of the second output and the third output for actuating the second switch.
With the objects of the invention in view, there is also provided a method for compensating for an offset in an input signal, including the steps of filtering an input signal utilizing a first time constant, forming an output signal having discrete states by comparing the filtered input signal with one of a threshold voltage and the input signal in unfiltered form, effecting a changeover to a second time constant longer than the first time constant in a setting mode if and for as long as the output signal has at least two identical, successive states, and setting the second time constant in a normal mode following the setting mode.
With the objects of the invention in view, there is also provided a method for compensating for an offset in an input signal, including the steps of generating a filtered output signal by filtering an input signal utilizing a first time constant, forming an output signal having discrete states by comparing the filtered output signal with one of a threshold voltage and the input signal in unfiltered form, effecting a changeover to a second time constant longer than the first time constant in a setting mode if and for as long as the output signal has at least two identical, successive states, and setting the second time constant in a normal mode following the setting mode.
The principle underlying the invention is that it is possible to change over between a first and a second time constant, and, hence, the offset in an input signal can be compensated for using a first comparator and a first decoder. In such a case, the first decoder can influence the first switch S1 as appropriate based upon the output signal""s bit train that is at the comparator output.
The input signal can be a sequential signal coded on a bit-by-bit basis. A decision threshold is determined by turning on the first switch in a setting mode, which means that a first time constant is active. When a suitable decision threshold has been set, the first switch can be turned off during a user data transmission and it is, thus, possible to change over to another, second time constant, which can be greater than the first time constant. However, the first switch can also be turned off during the actual setting of the decision threshold that precedes useful operation. This can be appropriate, for example, if the input signal has a succession of several identical states immediately succeeding one another. This is because these states would result in the decision threshold not being suitable for distinguishing between the state levels because the decision threshold would assume the value of one state, zero or one. This means that the principle described can also be applied for those signals whose preamble is short.
The first and second time constants can be produced using a respective low-pass filter or using a respective high-pass filter.
If low-pass filters are used, they can either be in analog form including a respective resistor and capacitor or can be implemented digitally.
To achieve faster or more accurate offset compensation, further time constants, comparators, and decoders can be provided.
The filtered input signal, which can be derived on a radio-frequency receiver, for example, can be supplied to the first comparator.
The principle described allows simple and reliable compensation for DC voltage offsets at a receiver output even if decoupling using series capacitors is not possible.
In addition, the filter unit has a third time constant and a second switch is used to change over to the third time constant. A second and a third comparator are connected downstream of the filter unit, and a second decoder is connected to a respective output of the second and third comparators, which output can be used to actuate the second switch. The second and third comparators together form a window comparator. As soon as the voltage value of the input signal exceeds an upper limit or undershoots a lower limit, then, to equalize quickly a very large DC voltage offset that exists, a second switch can change over to a third time constant, which is, preferably, less than the first and second time constants and can be used to compensate for the offset voltage quickly.
A second decoder connected to the output of the second and third comparators identifies any exceeding of an upper limit or any undershooting of a lower limit and connects the third time constant, possibly using the second switch.
The limit values for the window comparator can each be set using voltage sources. The upper limit should be situated somewhat above, and the lower limit should be situated somewhat below, the input voltage values arising with suitable selection of the threshold voltage.
All in all, the three switchable time constants provide the option of changing over from a mean time constant to a longer time constant during a user data transmission, on one hand, but, on the other hand, it is advantageously possible to change over to a long time constant even if further zeros or ones also occur in succession during determination of the decision threshold in the first comparator, which would, in such a case, result in the threshold value being corrupted if the mean time constant were retained.
The principle can be applied advantageously to the Bluetooth standard, for example. In that case, as described in the introduction, the preamble including an alternating string of zeros and ones is only 4 bits long, which means that the subsequent xe2x80x9caccess codexe2x80x9d needs to be used concomitantly for threshold-value determination. However, this code includes zeros and ones in a random order, which means that the threshold value would be corrupted if there were no changeover to a longer time constant for a succession of several zeros or several ones.
In accordance with another feature of the invention, the third time constant is less than the first time constant, which is less than the second time constant.
In accordance with a further feature of the invention, the high-pass filters form the time constants.
In accordance with an added feature of the invention, the low-pass filters form the time constants.
In accordance with an additional feature of the invention, an analog low-pass filter can be produced using a series resistor having a grounded capacitor connected downstream thereof. A plurality of RC elements for forming a plurality of time constants can have a common capacitor.
In accordance with yet another feature of the invention, an analog high-pass filter can be constructed using a series capacitor having a grounded resistor connected downstream thereof. A plurality of high-pass filters for forming a plurality of time constants can have a common capacitor.
In accordance with yet a further feature of the invention, high-pass filters or low-pass filters can be produced as digital filters. To this end, a delay element can be provided. In such a case, the first and second decoders can vary a gain factor in a feedback loop to influence the time constant of the digital filter.
In accordance with yet an added feature of the invention, it is possible to change over between the voltage of the input signal and a controlled voltage source. This can be appropriate, for example, if a plurality of identical binary states coded in the input signal succeed one another during determination of an offset compensation value, which means that the compensation value would be corrupted with the time constant that is set. With long sequences of identical bits immediately succeeding one another, switching back and forth between input voltage and controlled voltage is performed repeatedly.
In accordance with yet an additional feature of the invention, low-pass filters form the first, second, and third time constants, a first of the low-pass filters has a first resistor, the controlled voltage source produces a voltage, the filter unit produces a threshold voltage, and a voltage present across the first resistor is changeable over between the voltage of the input signal and the voltage of the controlled voltage source, the voltage of the controlled voltage source having twice the threshold voltage minus the input voltage.
In accordance with again another feature of the invention, a first of the low-pass filters has a first resistor, a controlled voltage source produces a voltage, the input signal has a voltage, the filter unit produces a threshold voltage, and a voltage present across the first resistor is changeable over between the voltage of the input signal and the voltage of the controlled voltage source, the voltage of the controlled voltage source having twice the threshold voltage minus the input voltage.
If the input signal is in the form of a differential signal, the input voltage can be changed over by reversing the polarity of the differential signal lines. This also makes it possible to avoid corruption of the compensation value as a result of a long succession of identical states in the input signal. The first decoder can detect a succession of identical states immediately succeeding one another and can carry out appropriate polarity reversal. If, by way of example, ten successive logic ones are coded, then the input signal in the form of a differential signal can have its polarity reversed after three respective bits.
In accordance with a concomitant mode of the invention, there are provided the steps of supplying the input signal to a window comparator having a second comparator and a third comparator, comparing a voltage of the input signal with an upper and a lower voltage limit value, and effecting a changeover to a third time constant if the upper voltage limit value is exceeded or the lower voltage limit value is undershot.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a compensation circuit and method for compensating for an offset, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.